🛠 Exploiter les deux cœurs et la FIFO inter-cœurs

Objectives

The RP2350 features two Arm Cortex-M33 cores (or two RISC-V Hazard3 cores, architecture selected at boot). This tutorial runs a producer on core 0 and a consumer on core 1, connected via the SDK's 32-entry hardware FIFO, and then via shared memory. This is the major difference compared to a single-core board.

Hardware

• 1 × Raspberry Pi Pico 2
• Pico SDK ≥ 2.0.0, compiled with -DPICO_BOARD=pico2
• Serial terminal on UART0 (GP0/GP1) for output

Complete code

/* multicore_fifo.c — coeur 0 produit, coeur 1 consomme via hardware/fifo */
#include "pico/stdlib.h"
#include "pico/multicore.h"
#include <stdio.h>

#define LED_PIN 25

void coeur1(void) {                /* execute sur le deuxieme M33 */
    gpio_init(LED_PIN); gpio_set_dir(LED_PIN, GPIO_OUT);
    uint32_t somme = 0, n = 0;
    while (true) {
        uint32_t v = multicore_fifo_pop_blocking;  /* attend une donnee */
        somme += v; n++;
        if (n == 100) {
            gpio_put(LED_PIN, !gpio_get(LED_PIN));
            multicore_fifo_push_blocking(somme);     /* rapporte la somme */
            somme = 0; n = 0;
        }
    }
}

int main(void) {
    stdio_init_all;
    multicore_launch_core1(coeur1);   /* demarre le coeur 1 */
    uint32_t tick = 0;
    while (true) {
        multicore_fifo_push_blocking(++tick);        /* 1..N */
        if (multicore_fifo_rvalid) {               /* rapport pret ? */
            printf("somme des 100 derniers = %u\n",
                   multicore_fifo_pop_blocking);
        }
        sleep_ms(1);
    }
}

Expected verification

The LED pulses every 100 values, and the terminal displays increasing sums (100·n + 5000 per window). Set a breakpoint or an occupied loop in coeur1: core 0 continues running — proof that the two M33 cores execute in true parallel.

Common errors

• Calling multicore_fifo_pop_blocking on both sides without synchronization: data loss, as the FIFO has only 32 slots and does not distinguish senders.
• Using shared global variables without __attribute__((aligned(4))) or a lock: byte-by-byte accesses are not atomic between cores; prefer spin_lock (hardware/sync.h).
• Forgetting that core 1 does not start on its own: without multicore_launch_core1, only the main function executes.
• Confusing it with the RISC-V architecture: if booting in Hazard3 mode, the ARM multicore SDK does not apply as-is.
• Using printf from both cores simultaneously: unreadable interleaving; centralize I/O on one core.