🛠 Horodatage industriel : PTP IEEE 1588 sur le PHY Ethernet du CM4
Objectives
A unique feature in the Pi range: the CM4 embeds a Gigabit Ethernet PHY compatible with IEEE 1588 (PTP) on the module — designed for industrial real-time synchronization (flagship cards use discrete PHYs without this claim). This tutorial sets up a two-node PTP domain with linuxptp: one grandmaster, one slave, and measures the residual offset in microseconds.
Hardware
- 2 × CM4 (with Ethernet, so not a CM4S) on an IO Board, running 64-bit Raspberry Pi OS
- 1 straight-through Ethernet cable between the two RJ45 ports (direct topology: a non-transparent switch significantly degrades precision)
- Separate control network (Wi-Fi or second port) for SSH configuration
sudo apt install -y linuxptpon both nodes
Complete code
# --- Nœud A : grandmaster ---
sudo tee /etc/linuxptp/master.conf >/dev/null <<'EOF'
[global]
slaveOnly 0
networkTransportAddress eth0:500
summaryRatio -1
syncInterval 0
EOF
sudo ptp4l -f /etc/linuxptp/master.conf -m &
# --- Nœud B : esclave ---
sudo tee /etc/linuxptp/slave.conf >/dev/null <<'EOF'
[global]
slaveOnly 1
networkTransportAddress eth0:500
EOF
sudo ptp4l -f /etc/linuxptp/slave.conf -m &
# Ajuste CLOCK_REALTIME depuis la hardware clock de eth0
sudo phc2sys -s eth0 -c CLOCK_REALTIME -O 0 -m &
# --- Sur l'esclave : interroger l'état de synchronisation ---
sudo pmc -u -b eth0 'GET TIME_STATUS_NP' | grep -E 'master_offset|gmIdentity'
Expected verification
In the output of ptp4l -m on the slave side, the master offset lines converge to values in the order of microseconds in a direct topology; pmc 'GET TIME_STATUS_NP' displays a stable master_offset and the grandmaster identity; phc2sys no longer reports jumps. The two date commands at both ends agree to within a millisecond.
Common errors
- Going through a home switch: without transparent PTP support, traversal asymmetry causes the offset to plateau at hundreds of microseconds or more.
- Trying to run PTP over Wi-Fi: the wireless medium (CYW43455) does not offer timestamp stability; only the wired PHY is covered by 1588 compatibility.
- Forgetting
phc2sys: PTP synchronizes the interface's hardware clock, not CLOCK_REALTIME; without this daemon,datedoes not change. - Conflict with systemd-timesyncd/NTP: disable
sudo timedatectl set-ntp falseon the slave, otherwise NTP constantly "corrects" the PTP offset.
Other tutorials for this board
- Premier démarrage d'un CM4 Lite depuis la microSD de l'IO Board
- GPIO du CM4 : comprendre les banks 1,8 V / 3,3 V avant de câbler
- Basculer le Wi-Fi du CM4 sur l'antenne externe U.FL (dtparam=ant2)
- Bootloader EEPROM du CM4 : maîtriser BOOT_ORDER via usbboot
- Ajouter une RTC au CM4 (PCF8523 sur I2C1 via dt-blob)
- Son sur CM4 : DAC I2S/PCM (PCM5102) sans prise jack
Code examples for this board
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